Processor and event processing method

ABSTRACT

An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of InternationalApplication No. PCT/JP2019/35804, filed on Sep. 12, 2019, the entirecontents of which are incorporated herein by reference.

BACKGROUND

The disclosure relates to a processor that performs event processing andan event processing method.

An event processing unit (EPU) is used as a processor (an arithmeticunit) that executes various event processing instead of the main CPU.The EPU includes multiple hardware contexts (hereinafter referred to asthreads) consisting of a program counter (PC), a general-purposeregister, etc., and is configured to select a thread according to thepriority and execute a sequence corresponding to the thread in a singlearithmetic unit (For example, see Japanese Patent Publication No.2019-101543 (Patent Document 1)). The sequence corresponding to thethread is stored in a program memory and indicates a location (address)in the program memory where the PC of each thread is to be executed. Thearithmetic unit reads (fetches) a program code from the address in theprogram memory indicated by the PC of the selected thread and executesan operation corresponding to the code.

The EPU is input with an event for each thread. When an event is inputand enabled, each thread enters in a RUN status, in which an instructionis being executed or requested to be executed, and a WAIT status, inwhich the execution of an instruction is being waited. The transitionfrom the RUN status to the WAIT status is caused by an instructionexecuted by the thread. The transition from the WAIT status to the RUNstatus occurs when an event input to the thread occurs, or when the timemeasured by an internal timer has elapsed. The EPU controls the startand stop of the instruction execution for each thread according to theinstruction and event input, and executes a necessary instruction whennecessary.

An instruction that transitions a thread to the WAIT status is anEVTWAIT instruction. The EVTWAIT instruction includes an input eventnumber in an operand. When an EVTWAIT instruction is executed, thethread transitions from the RUN status to the WAIT status, and when anevent corresponding to the specified input event number occurs, thethread transitions from the WAIT status to the RUN status.

SUMMARY

Measurement of the time to return to the RUN status may be requiredafter an EVTWAIT instruction is executed. For example, when the load onthe power supply is light, an intermittent operation is realized by theWAIT status by an EVTWAIT instruction and a restart operation by anevent input from a detection mechanism that detects a drop in an outputpower supply voltage in an EPU used in a power supply system thatoperates intermittently to achieve low power consumption. In this case,the load during standby is estimated by measuring the time betweenstandby and restart of the power supply, which may be used for adetermination of switching from an intermittent operation to a normaloperation.

Currently, the time between standby and restart is measured by startingan external timer before an EVTWAIT instruction is executed andreferring to a count value of the timer immediately after restart. Thismethod consumes an external timer resource, and the time required tocontrol the external timer directly affects the program size andexecution time of a thread. The processing time may not be ignored in apower supply system that requires strict real-time performance, where acontrol loop may have to be executed in hundreds of ns.

In a processor and an event processing method according to one or moreembodiments, the time to return to the RUN status after execution of anEVTWAIT instruction may be measured in real time without consuming anexternal timer resource.

A processor according to one or more embodiments is disclosed thattransitions from an execution status, in which an instruction is beingexecuted or requested to be executed, to a wait status, in which aninstruction is waiting to be executed, by an event wait instructionspecifying a wait event, and transitions from the wait status to theexecution status by an occurrence of the wait event. The processor mayinclude a timer counter that increments a counter value from an initialvalue; an event input control unit that detects an event input, whichnotifies the occurrence of an event; a wait event detection unit thatdetects the wait event by the event input; a status control unit thatchanges a status from the execution status to the wait status andoutputs a count start signal to instruct the timer counter to startcounting by the event wait instruction, and changes a status from thewait status to the execution status and outputs a count end signal toinstruct the timer counter to end counting by the detection of the waitevent; and a measurement value register that receives and stores a countvalue of the timer counter by output of the count end signal from thestatus control unit.

An event processing method of a processor according to one or moreembodiments is disclosed that transitions from an execution status, inwhich an instruction is being executed or requested to be executed, byan event wait instruction specifying a wait event, and transitions fromthe wait status to the execution status by an occurrence of the waitevent. The method may include detecting an event input, which notifiesan occurrence of an event; detecting the wait event by the event input;changing a status from the execution status to the wait status andoutputs a count start signal by the event wait instruction, and changesa status from the wait status to the execution status and outputs acount end signal by the detection of the wait event; incrementing acounter value from an initial value by output of the count start signal,and ends counting by output of the count end signal; and receiving inand storing the count value by output of the count end signal.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a processoraccording to one or more embodiments;

FIG. 2 is an explanatory diagram illustrating status transitions of athread, such as is illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a detailed configuration of aprocessor core, a thread selection control unit, and an event controlunit within a thread, such as is illustrated in FIG. 1;

FIG. 4 is a flowchart illustrating an operation of a processor, such asis illustrated in FIG. 1, by an EVTWAIT instruction with a request tomeasure a WAIT period;

FIG. 5 is an explanatory diagram illustrating an operation of a countertimer, such as is illustrated in FIG. 1;

FIG. 6 is an explanatory diagram illustrating an example of anapplication of a processor to a power supply system according to one ormore embodiments;

FIG. 7 is a flowchart illustrating an operation of a processor, such asis illustrated in FIG. 1, by a MEVTWAIT instruction with a request tomeasure a WAIT period; and

FIGS. 8A and 8B are explanatory diagrams illustrating operations of acounter timer, such as is illustrated in FIG. 1.

DETAILED DESCRIPTION

A processor that performs event processing and an event processingmethod according to one or more embodiments are explained with referringto drawings. In the respective drawings referenced herein, the sameconstituents are designated by the same reference numerals and duplicateexplanation concerning the same constituents may be omitted. All of thedrawings are provided to illustrate the respective examples only. Nodimensional proportions in the drawings shall impose a restriction onthe embodiments. For this reason, specific dimensions and the likeshould be interpreted with the following descriptions taken intoconsideration. In addition, the drawings include parts whose dimensionalrelationships and ratios are different from one drawing to another.

A processor 1 according to one or more embodiments may be an eventprocessing unit (EPU) that executes various event processing as analternative to a host system, such as the main CPU, which is notillustrated in the figure. In FIG. 1, the processor 1 includes two ofthread 2 (2 ₀, 2 ₁), a processor core 3, a thread selection control unit4, a system bus slave I/F 5, a system bus master 6, an instructionmemory access I/F 7, a data memory access I/F 8, and a memory 9. Theprocessor 1 illustrated in FIG. 1 illustrates two of thread 2, but thenumber of the thread 2 is not limited thereto.

The thread 2 includes a 32-bit general-purpose register group includinggeneral-purpose registers R0 to R15, a storage area ACC for storing thetotal of 64-bit operations, a 9-bit counter timer TMR, a setting areaPRESCALER for setting the count timing of the counter timer TMR, asetting area FPU flag/mode for setting an operation mode and a status ofa 32-bit floating-point arithmetic unit (FPU), a stack pointer SP, aprogram counter PC, a carry flag C for a calculation result, and acomparison result holding area T as contexts. In addition to theabove-described contexts, the thread 2 includes an event control unit 21that controls input and output events. Except for the counter timer TMRand the event control unit 21, which are essential to the presentdisclosure, the components of the thread 2 may be configured in anygeneral-purpose CPU.

The processor core 3 includes a mechanism for fetching an instructioncode from the memory 9, an instruction decoder for interpreting thefetched code to determine what kind of instruction the fetched code is,an arithmetic unit, and a mechanism for processing a data accessinstruction. The processor core 3 includes an integer arithmetic unitINT and a floating-point arithmetic unit FPU as arithmetic units. Theinteger arithmetic unit INT includes an addition/subtraction logicoperational circuit ALU, a comparison circuit CMP, and a multiplier MUL.The floating-point arithmetic unit FPU includes an adder-subtractor ADD,a divider DIV, and a multiplier MUL. An operation is performed bycombining components of the integer arithmetic unit INT and thefloating-point arithmetic unit FPU according to an instruction.

The data access instruction includes a register-to-register accessinstruction, a memory access instruction, and a system bus accessinstruction. The processor core 3 transfers data between registers viathe thread selection control unit 4 by the register-to-register accessinstruction. The processor core 3 reads data from the memory 9 andwrites data to the memory 9 via the data memory access I/F 8 by thememory access instruction. The processor core 3 reads or writes tovarious peripheral modules connected to the system bus 10 via the systembus master 6 by the system bus access instruction.

The thread selection control unit 4 selects one thread from aninstruction execution request from each thread 2 (2 ₀, 2 ₁) according toa priority order and passes the context to the processor core 3. Thepriority may be a fixed priority (e.g., the smaller the thread numberis, the higher the priority is), a round robin (a method of circulatingthe priority between two threads by setting the priority of the threadimmediately after execution is stopped to be the lowest), or a mixedmethod of the fixed priority and round robin.

The system bus slave I/F 5 is an interface between the thread 2 (2 ₀, 2₁) and the system bus 10, and handles access from a host system, such asthe main CPU, etc., via the system bus 10. Context initialization,operation start/stop, and program placement in the memory are alsoperformed via the system bus slave I/F 5.

The system bus master 6 is an interface between the processor core 3 andthe system bus 10, and controls access to the system bus 10 according toa system bus access instruction issued by the processor core 3.

The instruction memory access I/F 7 is an interface between theprocessor core 3 and the memory 9, receives a fetch instruction requestand a fetch address from the processor core 3, and accesses the memory9.

The data memory access I/F 8 is an interface between the processor core3 and the memory 9, and controls access to the memory 9 according to adata memory access instruction issued by the processor core 3. The datamemory access I/F 8 also handles memory access from the system bus slaveI/F 5. Therefore, the data memory access I/F 8 mediates access from theprocessor core 3 and the system bus 10.

The memory 9 is a storage area that stores a program and data forexecuting an event. In the embodiment, instructions and data are storedin the single memory 9. The memory 9 includes a read-only 1 portconnected to the instruction memory access I/F 7 and a read-write 1 portconnected to the data memory access I/F 8.

In FIG. 2, the thread 2 transitions among a STOP status (a stop status),a RUN status (an execution status) where an instruction is beingexecuted or requested to be executed, and a WAIT status (a wait status)where an instruction is waiting to be executed. The thread 2 in the STOPstatus does not issue a request for instruction execution and stops. Thethread 2 is in the STOP status during initialization, such as reset,etc. The thread 2 in the RUN status outputs a request for instructionexecution. The thread 2 selected by the thread selection control unit 4accepts the instruction execution request, and the arithmetic unit (theprocessor core 3) executes the instruction. The thread 2 in the WAITstatus temporarily stops instruction execution.

The status transition from the STOP status to the RUN status is causedby a setting in a control register from the host system, such as themain CPU, etc., or an enabling instruction from another thread 2. Thestatus transition from the RUN status to the WAIT status is caused by anEVTWAIT instruction (an event wait instruction) or a MEVTWAITinstruction (a multiple event wait instruction). The status transitionfrom the WAIT status to the RUN status is caused by the detection of theoccurrence of a wait event. The status transitions from the RUN statusto the STOP status and from the WAIT status to the STOP status arecaused by a setting in a control register of the EPU from the hostsystem, such as the main CPU, etc., or a disabling instruction fromanother thread 2.

FIG. 3 illustrates a detailed configuration of the processor core 3, thethread selection control unit 4, and the thread 2 (an event control unit21).

The processor core 3 fetches an instruction code of a thread selected bythe thread selection unit 4 from the memory 9 in a fetch instructionmechanism, which is not illustrated in the figure, and keeps theselected thread as thread identification information. The instructioncode is separated into an opcode (opcode) and an operand (oprand). Theopcode indicates a type of an instruction, and the operand indicates thedata and information associated with an instruction. The processor core3 includes an instruction decoder 31. The instruction decoder 31 decodesthe opcode, and outputs an EVTWAIT signal to indicate that theinstruction is an EVTWAIT instruction when the instruction code is anEVTWAIT instruction, and outputs a MEVTWAIT signal to indicate that theinstruction is a MEVTWAIT instruction when the instruction code is aMEVTWAIT instruction. The instruction decoder 31 decodes the opcode andalso outputs a TMR operation signal to indicate that the operation ofthe counter timer TMR is enabled if the instruction code requests themeasurement of the period when the instruction code is in the WAITstatus (hereinafter referred to as the WAIT period). In the case of anEVTWAIT instruction, the operand becomes the wait event information toindicate which event is to be waited for. In the case of a MEVTWAITinstruction, the operand becomes the selection information of the returnstatus storage location to select a register to store the return status.

The thread selection control unit 4 selects the thread 2 to execute aninstruction code based on the thread identification information, andsends the wait event information, an EVTWAIT signal, a MEVTWAIT signal,a TMR operation signal, and a return status storage location selectionsignal to the selected thread 2.

The event control unit 21 of the thread 2 includes a TMRSET register 22,a TMRCAP register 23, an EVTSTS register 24, and an EVTSEL register 25,which operate as an event input control unit 26, an EVTWAIT instructiondetection unit 27, a MEVTWAIT event control unit 28, a MEVTWAITinstruction detection unit 29, and a status control unit 30.

The counter timer TMR loads an initial value set in the TMRSET register22 as a count value by a count start signal from the status control unit30. The initial value is set in the TMRSET register 22 from the hostsystem via the system bus slave I/F 5. The initial value may also beincluded in the operand of an instruction code and set for eachinstruction code.

The counter timer TMR counts down the count value at the countdowntiming set in the PRESCALER by a countdown signal from the statuscontrol unit 30. The counter timer TMR outputs a timer event when thecount value becomes 0 by the countdown signal.

The TMRCAP register 23 imports the count value of the counter timer TMRby a count end signal from the status control unit 30.

The EVTSTS register 24 is a status register with one bit allocated foreach event, and operates as the event input control unit 26, whichdetects an event that has occurred. The event input (occurrence of anevent) causes the corresponding status bit in the EVTSTS register 24 tobe set to 1, thereby detecting an event that has occurred. In additionto an input from an external function module, the event input includes atimer event output from the counter timer TMR. A status clear signaloutput from the status control unit 30 sets the corresponding status bitin the EVTSTS register 24 from 1 to 0, indicating that no event has beendetected.

The EVTWAIT instruction detection unit 27 waits for a status bit of theEVTSTS register 24 corresponding to a wait event to be set to 1 by adetection start signal from the status control unit 30. When the EVTWAITinstruction detection unit 27 detects a status bit of the EVTSTSregister 24 corresponding to a wait event is 1, the EVTWAIT instructiondetection unit 27 outputs a detection signal to the status control unit30.

The EVTSEL register 25 is a status register with one bit allocated foreach event, and is set with multiple events to be waited for by aMEVTWAIT instruction. The EVTSEL register 25 is set by the host systemvia the system bus slave I/F 5. The setting of the EVTSEL register 25may also be included in the operand of an instruction code and set foreach instruction code.

The EVTSEL register 25 operates with a selection unit 281, which selectsan event to be waited for by performing a bitwise AND operation betweenthe EVTSTS register 24 and the EVTSEL register 25, and an event prioritycontrol unit 282, which performs priority control when multiple eventsto be waited for are detected simultaneously, as the MEVTWAIT eventcontrol unit 28, which detects the occurrence of an event waited for bya MEVTWAIT instruction to output to the MEVTWAIT instruction detectionunit 29. Hereinafter, an event detected by the MEVTWAIT event controlunit 28 is referred to as a MEVTWAIT event. The priority control by theevent priority control unit 282 may be a predetermined fixed priority, around robin, or a mixed method of the fixed priority and round robin,etc.

The MEVTWAIT instruction detection unit 29 waits for the detection of aMEVTWAIT event by the MEVTWAIT event control section 28 by a detectionstart signal from the status control section 30. When a MEVTWAIT eventis detected by the EVTWAIT event control unit 28, the MEVTWAITinstruction detection unit 29 outputs a detection signal to the statuscontrol unit 30 and outputs the return event identification informationto the general-purpose register group R0 to R15 as information toidentify the detected MEVTWAIT event.

The general-purpose register group R0 to R15 receives a return statuswrite signal from the status control unit 30 specifying the returnstatus storage location (one of the registers R0 to R15), and writes thereturn event identification information to one of the specifiedregisters R0 to R15. Thus, by confirming the return event identificationinformation after returning from the MEVTWAIT instruction, which eventhas returned after the MEVTWAIT instruction may be determined, andswitching the processing after returning may be conducted.

The status control unit 30 outputs a detection start signal to theEVTWAIT instruction detection unit 27 by an EVTWAIT signal, and changesthe thread 2 from the RUN status to the WAIT status. The status controlunit 30 changes the thread 2 from the WAIT status to the RUN status by adetection signal from the EVTWAIT instruction detection unit 27,restarts the thread's instruction execution, and outputs a status clearsignal to the EVTSTS register 24.

The status control unit 30 outputs a detection start signal to theMEVTWAIT instruction detection unit 29 by a MEVTWAIT signal, and changesthe thread 2 from the RUN status to the WAIT status. The status controlunit 30 changes the thread 2 from the RUN status to the WAIT status by adetection signal from the MEVTWAIT instruction detection unit 29,restarts the thread's instruction execution, outputs a status clearsignal to the EVTSTS register 24, and outputs a return status writesignal specifying the return status storage location to thegeneral-purpose register group R0 to R15.

When a TMR operation signal is input along with an EVTWAIT signal or aMEVTWAIT signal, the status control unit 30 outputs a counting startsignal. The status control unit 30 outputs a countdown signal during theWAIT status, and outputs a count end signal at the transition from theWAIT status to the RUN status.

An operation of the processor 1 by an EVTWAIT instruction with ameasurement request for a WAIT period is explained in detail withreference to FIG. 4 and FIG. 5.

In FIG. 4, the processor core 3 fetches an instruction code from amemory address indicated by the program counter PC of the threadselected by the thread selection control unit 4 (step S101), and keepsthe selected thread number as thread identification information.

The instruction decoder 31 of the processor core 3 decodes an opcode andoutputs an EVTWAIT signal, which indicates an EVTWAIT instruction, and aTMR operation signal, which indicates that the operation of the countertimer TMR is enabled, to the thread selection control unit 4 (stepS102).

The processor core 3 outputs the thread identification information andthe wait event information of the operand to the thread selectioncontrol unit 4 (step S103).

The thread selection control unit 4 selects the thread 2 to execute aninstruction code based on the thread identification information, sendsthe wait event information to the EVTWAIT instruction detection unit 27of the selected thread 2 (step S104), and sends an EVTWAIT signal and aTMR operation signal to the status control unit 30 (step S105).

The status control unit 30 outputs a detection start signal to theEVTWAIT instruction detection unit 27 by the EVTWAIT signal and changesthe thread 2 from the RUN status to the WAIT status (step S106).

The status control unit 30 outputs a count start signal by the TMRoperation signal and a countdown signal during the WAIT status to thecounter timer TMR (step S107).

As illustrated in FIG. 5, by the count start signal, the initial value Xset in the TMRSET register 22 is loaded in the counter timer TMR as acount value. The count value of the counter timer TMR is counted down atthe countdown timing set in the PRESCALER by a countdown signal inputduring the WAIT status.

By the detection start signal from the status control unit 30, theEVTWAIT instruction detection unit 27 waits for the status bit of theEVTSTS register 24 corresponding to the wait event to be 1, that is,waits for the occurrence of a wait event (step S108).

When the status bit of the EVTSTS register 24 corresponding to the waitevent becomes 1 in the step S108, the EVTWAIT instruction detection unit27 outputs a detection signal to the status control section 30 (stepS109).

By the detection signal from the EVTWAIT instruction detection unit 27,the status control section 30 changes the status of the thread 2 fromthe WAIT status to the RUN status to execute the process correspondingto the EVTWAIT instruction (step S110), outputs a count end signal tothe TMRCAP register 23 (step S111), and outputs a status clear signal tothe EVTSTS register 24 to terminate the event wait operation (stepS112).

As illustrated in FIG. 5, by the count end signal, a count value Y ofthe counter timer TMR at the time of the input of the count end signalis captured to the TMRCAP register 23. Therefore, the host system maygrasp the WAIT period by referring to the count values in the TMRSETregister 22 and the TMRCAP register 23. In other words, a value, whichis obtained by multiplying the difference between the initial value X ofthe TMRSET register 22 and the count value Y+1 captured in the TMRCAPregister 23 by a countdown cycle, may be measured as the WAIT periodfrom the execution of the EVTWAIT instruction to the detection of a waitevent. The reset timing of the TMRCAP register 23 may be set by the hostsystem as appropriate.

In a power supply system, as illustrated in FIG. 6, a PWM output isoperated intermittently to reduce power consumption when the load on thepower supply is light. When a drop in output current is detected at atime t₀, the light load is recognized, and the power supply control isstopped. Then, the output voltage drops according to the chargecapacitance of an output capacitor. When the output voltage falls belowa threshold voltage V_(th) at a time t₁, the power supply control isrestarted to recover the output voltage. The intermittent operation isexpected to improve the efficiency because no switching operation by thepower supply control occurs during the period when the power supplycontrol is stopped.

The intermittent operation may be realized by the WAIT status by anEVTWAIT instruction and a restart operation (the RUN status) by theevent input from a detection mechanism of the output voltage drop. Inthis case, the EVTWAIT instruction, in which the drop in the outputvoltage to the threshold voltage V_(th) is a wait event, is input to theprocessor 1 at the time t₀ when the drop in output current is detected,and the processor 1 changes to the WAIT status.

A wait event is detected at the time t₁ when a drop in the outputvoltage to the threshold voltage V_(th) is detected. As a result, apower control stop period from the time t₀ to time t₁ is measured as theWAIT period. The current consumption during the wait period may beestimated from the power control stop period, drop voltage, and externalload capacitance. Therefore, it may be possible to estimate the loadduring standby and use the estimation in a decision to switch from theintermittent operation to the normal operation, and control may beperformed to improve efficiency at light loads.

Referring to FIG. 7, the processor core 3 fetches an instruction codefrom a memory address indicated by the program counter PC of the threadselected by the thread selection control unit 4 (step S201), and keepsthe selected thread number as thread identification information.

The instruction decoder 31 of the processor core 3 decodes an opcode,and outputs a MEVTWAIT signal indicating a MEVTWAIT instruction and aTMR operation signal indicating that an operation of the counter timerTMR is enabled to the thread selection control unit 4 (step S202).

The processor core 3 outputs the thread identification information andreturn status storage selection information of the operand to the threadselection control unit 4 (step S203).

The thread selection control unit 4 selects the thread 2 to execute theinstruction code based on the thread identification information, andsends the MEVTWAIT signal and the TMR operation signal to the statuscontrol unit 30 (step S204). In the EVTSEL register 25, multipleMEVTWAIT events to be waited for by the MEVTWAIT instruction by the hostsystem and a timer event are stored in the EVTSEL register 25 (stepS205).

By the MEVTWAIT signal, the status control unit 30 outputs a detectionstart signal to the MEVTWAIT instruction detection unit 29, and changesthe status of the thread 2 from the RUN status to the WAIT status (stepS206).

By the TMR operation signal, the status control unit 30 outputs a countstart signal and the countdown signal during the WAIT status to thecounter timer TMR (step S207).

As illustrated in FIGS. 8A and 8B, by the count start signal, theinitial value X set in the TMRSET register 22 is loaded to the countertimer TMR as a count value. The count value of the counter timer TMR iscounted down at the countdown timing set in the PRESCALER by thecountdown signal input during the WAIT status.

By the detection start signal from the status control section 30, theMEVTWAIT instruction detection unit 29 waits for the detection of aMEVTWAIT event by the MEVTWAIT event control unit 28, that is, theoccurrence of one of the multiple MEVTWAIT events to be waited for (stepS208), and waits for the detection of a timer event by the MEVTWAITevent control unit 28 (step S209).

When the MEVTWAIT event is detected by the MEVTWAIT event control unit28 in the step S208, the MEVTWAIT instruction detection unit 29 outputsa detection signal to the status control unit 30 (step S210), andoutputs the return event identification information to thegeneral-purpose register group R0 to R15 as information to identify thedetected MEVTWAIT event (step S211).

By the detection signal from the MEVTWAIT instruction detection unit 29,the status control unit 30 outputs a return status write signal thatspecifies the return status storage location to the general-purposeregister group R0 to R15 (step S212). As a result, the return eventidentification information from the MEVTWAIT instruction detection unit29 is written into one of the general-purpose registers R0 to R15specified by the return status write signal.

By the detection signal from the MEVTWAIT instruction detection unit 27,the status control section 30 changes the status of the thread 2 fromthe WAIT status to the RUN status to execute the process correspondingto the MEVTWAIT instruction (step S213). When executing a process, theprocess may be switched according to an event that occurred by referringto the return event identification information written in one of thegeneral-purpose registers R0 to R15.

The status control unit 30 outputs a count end signal to the TMRCAPregister 23 (step S214), and outputs a status clear signal to the EVTSTSregister 24 (step S215) to terminate the event wait operation.

As illustrated in FIG. 8A, by the count end signal, a count value Y ofthe counter timer TMR at the time of the input of the count end signalis captured into the TMRCAP register 23. Therefore, the host system maygrasp the WAIT period by referring to the count values of the TMRSETregister 22 and the TMRCAP register 23. In other words, a value, whichis obtained by multiplying the difference between the initial value X ofthe TMRSET register 22 and the count value Y+1 captured in the TMRCAPregister 23 by a countdown cycle, may be measured as the WAIT periodfrom the execution of the EVTWAIT instruction to the detection of a waitevent. The reset timing of the TMRCAP register 23 may be set by the hostsystem as appropriate.

As illustrated in FIG. 8B, when the count value of the counter timer TMRbecomes 0 and the timer event is detected by the MEVTWAIT event controlunit 28 in the step S209, the MEVTWAIT instruction detection unit 29outputs a detection signal to the status control unit 30 (step S216) andoutputs the return event identification information specifying thedetected timer event to the general-purpose register group R0 to R15(step S217).

By the detection signal from the MEVTWAIT instruction detection unit 27,the status control section 30 outputs a return status write signal thatspecifies the return status storage location to the general-purposeregister group R0 to R15 (step S218). As a result, the return eventidentification information from the MEVTWAIT instruction detection unit29 is written into one of the general-purpose registers R0 to R15specified by the return status write signal.

By the detection signal from the MEVTWAIT instruction detection unit 27,the status control unit 30 changes the status of the thread 2 from theWAIT status to the RUN status to execute the process corresponding tothe timer event (step S219). When executing the process, the processcorresponding to the timer event may be executed by referring to thereturn event identification information written in one of the specifiedgeneral-purpose registers R0 to R15.

The status control unit 30 outputs a status clear signal to the EVTSTSregister 24 (step S220) to terminate the event wait operation. Note thatthe status control unit 30 also outputs the count end signal to theTMRCAP register 23. However, since the count value of the counter timerTMR is 0, no change occurs in the TMRCAP register 23.

Therefore, a condition when a wait event that is being waited for by aMEVTWAIT instruction does not occur after waiting for a certain periodof time is recognized, and a process corresponding to a timer event thatis different from the normal processing may be executed. The time thatis obtained by multiplying the initial value X set in the TMRSETregister 22 by the countdown cycle is a timeout period to wait for aMEVTWAIT event.

As described above, the processor 1 according to one or more embodimentstransitions from the RUN status (the execution status), in which aninstruction is being executed or requested to execute, to the WAITstatus (the wait status), in which an instruction is waiting to beexecuted, by an EVTWAIT instruction (the event wait instruction), whichspecifies a wait event, and transitions from the WAIT status to the RUNstatus by the occurrence of a wait event. The processor 1 includes: thetimer counter TMR that starts counting from an initial value; the eventinput control unit 26 that detects the event input notifying theoccurrence of an event; the EVTWAIT instruction detection unit 27 (thewait event detection unit) that detects a wait event by the event input;the status control unit 30, which changes the status from the RUN statusto the WAIT status by the EVTWAIT instruction to output a count startsignal to instruct the timer counter TMR to start counting and changesthe status from the WAIT status to the RUN status by the detection of await event to output a count end signal to instruct the timer counterTMR to end counting; and the TMRCAP register 23 (the measurement valueregister), which takes in and holds the count value of the timer counterTMR by the output of the count end signal from the status control unit30.

The configuration may allow the host system to grasp the WAIT period byreferring to the count values of the TMRSET register 22 (the initialvalue) and the TMRCAP register 23, and the time to return to the RUNstatus after execution of an EVTWAIT instruction (the WAIT period) maybe measured in real time without consuming an external timer resource.

The status control section 30 according to one or more embodimentschanges the status from the RUN status to the WAIT status by a MEVTWAITinstruction (a multiple event wait instruction) specifying multiple waitevents, and outputs a count start signal that instructs the timercounter TMR to start counting. Also, the status control unit 30 changesthe status from the WAIT status to the RUN status by detecting one ofthe multiple wait events specified by the MEVTWAIT instruction from theMEVTWAIT instruction detection unit 29 (the wait event detection unit),and outputs a count end signal to instruct the timer counter TMR to stopcounting.

The configuration may allow multiple events to be specified as waitevents.

The timer counter TMR according to one or more embodiments outputs atimer event as an event input when the count value reaches a set value,and the MEVTWAIT instruction detection unit 29 detects the timer eventas one of the multiple wait events.

The configuration may recognize a condition when a wait event does notoccur even after waiting for a certain period of time.

The processor according to one or more embodiments includes thegeneral-purpose registers R0 to R15 (the identification informationregisters) that hold the wait event identification information, whichspecifies a wait event detected by the MEVTWAIT instruction detectionunit 29.

With the configuration, the wait event identification information heldin the general-purpose registers R0 to R15 may be used to recognize thewait event that has occurred, and a process may be switched by the waitevent that has occurred.

In the processor and the event processing method according to one ormore embodiments, the host system may measure the time to return to theexecution status after the execution of an event wait instruction byreferring to the count values of the initial value and the measurementvalue register in real time without consuming an external timerresource.

The present invention may not be limited to the above-describedembodiments, and that each embodiment may be changed as appropriatewithin the scope of the technical concept of the present invention. Thenumber, position, shape, etc. of the above-described components may notbe limited to the above-described embodiments, and may be made into anumber, position, shape, etc. suitable for implementing the presentinvention. The same sign is assigned to the same component in eachfigure.

1: Processor 2: Thread

3: Processor core4: Thread selection control unit5: System bus slave I/F6: System bus master7: Instruction memory access I/F8: Data memory access I/F

9: Memory

21: Event control unit22: TMRSET register23: TMRCAP register24: EVTSTS register25: EVTSEL register26: Event input control unit27: EVTWAIT instruction detection unit28: MEVTWAIT event control unit29: MEVTWAIT instruction detection unit30: Status control unit31: Instruction decoder

1. A processor that transitions from an execution status, in which aninstruction is being executed or requested to be executed, to a waitstatus, in which an instruction is waiting to be executed, by an eventwait instruction specifying a wait event, and transitions from the waitstatus to the execution status by an occurrence of the wait event,comprising: a timer counter that increments a counter value from aninitial value; an event input control unit that detects an event input,which notifies the occurrence of an event; a wait event detection unitthat detects the wait event by the event input; a status control unitthat changes a status from the execution status to the wait status andoutputs a count start signal to instruct the timer counter to startcounting by the event wait instruction, and changes a status from thewait status to the execution status and outputs a count end signal toinstruct the timer counter to end counting by the detection of the waitevent; and a measurement value register that receives and stores a countvalue of the timer counter by output of the count end signal from thestatus control unit.
 2. The processor according to claim 1, wherein thestatus control unit changes a status from the execution status to thewait status by a multiple event wait instruction that specifies the waitevent and outputs a count start signal to instruct the timer counter tostart counting, and changes a status from the wait status to theexecution status and outputs a count end signal to instruct the timercounter to end counting by the detection of one of the wait eventsspecified in the multiple event wait instruction.
 3. The processoraccording to claim 2, wherein the timer counter outputs a timer event asthe event input when a count value reaches a set value, and the waitevent detection unit detects the timer event as one of the wait events.4. The processor according to claim 2, further comprising: anidentification information register that holds wait event identificationinformation, which identifies the wait event detected by the wait eventdetection unit.
 5. The processor according to claim 3, furthercomprising: an identification information register that holds wait eventidentification information, which identifies the wait event detected bythe wait event detection unit.
 6. An event processing method of aprocessor that transitions from an execution status, in which aninstruction is being executed or requested to be executed, by an eventwait instruction specifying a wait event, and transitions from the waitstatus to the execution status by an occurrence of the wait event, themethod comprising: detecting an event input, which notifies anoccurrence of an event; detecting the wait event by the event input;changing a status from the execution status to the wait status andoutputs a count start signal by the event wait instruction, and changesa status from the wait status to the execution status and outputs acount end signal by the detection of the wait event; incrementing acounter value from an initial value by output of the count start signal,and ends counting by output of the count end signal; and receiving inand storing the count value by output of the count end signal.